The present invention relates to a semiconductor integrated circuit technology, and in particular, to a technology efficiently applicable to an input system of a test signal in an integrated logic circuit including a diagnosis circuit operating in the scanning method; furthermore, a technology is effectively applicable to a semiconductor integrated circuit device particularly having a great number of input/output pins such as a gate array circuit.
Recently, in a large scale integrated circuit device (LSI) formed on a semiconductor substrate, the number of input/output pins have been increased, for example, several hundred pins are disposed which is a considerable amount. In such a logic LSI having many input/output pins, diagnosis of the internal circuits thereof has become difficult because of the following reasons. That is, in the case where the LSI test is effected through the all-pin probe check, since the distance between pins is decreased when a great number of input/output pins (terminals) are provided, all probe pins cannot be easily brought into contact with all terminals (pads). Particularly, in an LSI employing a controlled collapse bonding (CCB) system as the pad structure, the contact between the pads and the probe pins cannot be readily established.
On the other hand, as a method of diagnosing a logic LSI, there has been proposed a scan method in which flip-flops disposed in the internal circuit are connected in series so as to operate the flip-flops as a shift register, thereby facilitating the test of the logic LSI ("Nikkei Electronics", the Nikkei-McGrowhill Co. Ltd., Apr. 16, 1979, pp. 57-79).
In the conventional diagnosis method employing the scan system, wirings must be designed to connect in series all flip-flops disposed in the internal circuit of the LSI, which results in a problem in that the number of designing steps is increased. Furthermore, although the diagnosis using the scan system facilitates the test of the logic circuit in a stage following the flip-flops, when testing the functions of logic gates in a range from the input circuit to the first flip-flop, a test signal must be inputted by connecting the probe to the input terminal through a separate operation. As a result, there has arisen the problem of the probe test becoming difficult in an LSI having a high terminal density. These problems have been overcome by the inventors of the present invention.